What is the Scalable Coherent Interface?

SCI is the modern equivalent of a Processor-Memory-I/O bus and a Local Area Network, combined and made parallel to support distributed multiprocessing with very high bandwidth, very low latency, and a scalable architecture that allows building large systems out of many inexpensive massproduced building blocks.

SCI originated as an offshoot from the IEEE Standard Futurebus+ project in 1988, when it became clear that coming microprocessors were soon going to be too fast for any bus, even Futurebus+, to support cost-effectively in multiprocessor configurations. The SCI group searched for some new approach that would provide familiar bus-like services to the user but avoid the bottlenecks inherent in physical buses; scale up to high-end supercomputer performance; and support efficient software for parallel-processing systems and applications.

A good solution was found, based on point-to-point links

Some happy side-effects were that:

SCI protocols were kept simple so interface chips could run fast, therefore interfaces have a low gate count and will be very inexpensive when volumes become high. Rethinking bus protocols to make them scalable and distance-independent also cleaned up a lot of messy areas that have historically made bus interface usage more expensive than necessary.

Transceivers and protocol logic and FIFOs all fit in a single chip and package. IBM reported at ISSCC '95 that their BiCMOS SCI-link chip receives 1000 Megabytes/s, transmits 1000 Megabytes/s, and communicates with user application logic all at the same time. It uses 36 signal pins for each of the two high speed SCI links, so pin count is low. No analog phase-locked-loop technology is needed, so the parts are easily manufactured and used in quantity. The IBM chip also dynamically compensates for cable skew, using SCI's standard deskewing protocol, so inexpensive cables can be used. Advanced CMOS processes are expected to be fast enough in 1995 that BiCMOS will no longer be needed for this speed.

There are no stub-length limitations whatsoever, so physical packaging is unconstrained by the requirements of a bus backplane--even extender cables can be used for convenient access during module maintenance, with virtually no chance that the behavior of the extended system will be different from that of the operational system and thus obscure the problem being studied, a serious problem for physical-bus-based systems.

Performance degrades only slowly as distance increases, so distributed systems like a ship or plane or campus can have integrated communication via SCI that is far faster than can be provided by any other open interconnect.

SCI's protocols allow local-area networking, but can eliminate the overheads-- recent benchmarks chosen by Sun show a 32-bit message ping-ponging between two Sparc machines in just 8 microseconds, using a slow (1000 Mbit/s) early CMOS version of SCI, connected via Sbus. That is 150 times less latency than achieved by previous network connections. Low latency is critically important for efficient distributed computing.

Adding nodes to an SCI system also adds bandwidth, so performance scales well.

Note the bandwidth comparison with other common technologies: One of today's 1 GByte/s (8000 Mbit/s) SCI links has about the same bandwidth as 64 of today's 155 Mbit/s ATM links, or 32 of today's FibreChannel 256 Mbit/s links, or 800 Ethernets, or 80 100baseT Ethernets. If SCI isn't fast enough, just add more links. If SCI is too fast, connect the links as a ring, sharing the excess link bandwidth with other nodes.

SCI supports switch interconnects arbitrarily intermixed with ring interconnects, offering an enormous range of cost/performance tradeoffs, and a convenient way for systems to evolve and grow over the years.

SCI's media-independent protocols allow transparent intermixing of copper and fiber links--for example, the SCI system can't tell the difference if a copper cable is replaced by optical fiber, such as Motorola's Optobus (which was designed to be a near-ideal match to SCI).

Serialbus shares much of the architectural model of SCI, as the two were deliberately designed to be conveniently interconnected. Serialbus is excellent for many I/O applications.

There is also a good chance that Serialbus (now in final weeks of completion) will adopt the scalable DMA architecture documented in draft standard P1285 Scalable Storage Interface, which was designed to scale over an enormous range of systems, like SCI. (P1285 S2I simplifies the basic disk controller, reducing costs even at the low end, while scaling upward smoothly to large highly parallel systems.)

However, Serialbus isn't by itself appropriate for the interconnection of distributed multiprocessors: it has fundamental distance limitations; it has the bus-inherent one-talker-at-a-time bottleneck problem (its cables are not independent links, but parts of a single distributed buffered bus); it has much lower bandwidth than SCI; and it offers no support for keeping cached data consistent

Early adopters of SCI include both commercial and military users.

In the commercial world, Convex Computer is now shipping their Exemplar supercomputer based on SCI, and most other computer companies are designing next-generation machines either with SCI or with a similar but deliberately incompatible interconnect. (Truly open standards are great for the consumer. They are also good for small-to-medium manufacturers, because the standards create a much larger market. However, a company that is dominant enough to impose its own "open" standard on a market segment can keep prices much higher for the year or two it takes competitors to get up to speed, and thus make far higher profits, so such a company will not use truly open standards until their customers insist.)

In the military world, the JAST (Joint Advanced Strike Technology-- Air Force, Navy, and Marines) has adopted SCI as the unified interconnect for a future fighter, instead of the 6 or 7 different interconnects as used in the F-22; the Society of Automotive Engineers video/sensors group has adopted it too; the Canadian Navy is using it as the interconnect for their Next Generation Signal Processor; and the Norwegian military is using SCI for advanced signal processors.

The preceding are the main aspects I thought would interest you from an open-systems viewpoint, but if you are really involved with multiprocessor architecture or parallel-system software there are many other good features you ought to know about. I didn't even start on the topics of security, reliability, fault tolerance, etc. etc.

SCI is truly an open standard, but still isn't widely known because early vendors in the field consider the few dozen computer companies to be their main customers, so there's little motivation to advertise; and the technology is so effective that those companies that have adopted SCI consider that fact to be a secret competitive advantage, so they mostly plan to say nothing until after their products have reached the market.